`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: University of Utah
// Engineer: David Hurst, Tyson Hunt, Chase Hochstrasser
// 
// Create Date:    16:10:54 09/08/2011 
// Design Name: 
// Module Name:    Regfile 
// Project Name: 
// Target Devices: 
// Tool versions: 
// Description: Create Registers to be used.
//
// Dependencies: 
//
// Revision: 
// Revision 0.01 - File Created
// Additional Comments: 
//
//////////////////////////////////////////////////////////////////////////////////
module Regfile(CLK, reset, rd_address1, rd_address2, read_data1, read_data2, wr_en, write_address, write_data, ballx, bally, p1, p2, p1_input, p2_input, p1_score, p2_score);

// Inputs
input CLK,reset,wr_en;
input [3:0] rd_address1, rd_address2, write_address;
input [15:0] write_data;



// Outputs
output [15:0] read_data1, read_data2;

// Register file
reg [15:0] regfile [0:15];

//VGA control inputs/outputs constantly read and write.
output reg [9:0] ballx;
output reg [8:0] bally;
output reg [8:0] p1, p2; //paddle
output reg [15:0] p1_score, p2_score; //paddle
input [11:0] p1_input;
input [11:0] p2_input;


// Always Block on Positive edge clock
always @(posedge CLK) begin
	regfile[4'he] <= p1_input;
	regfile[4'hf] <= p2_input;
	ballx <= regfile[4'h8];
	bally <= regfile[4'h9];
	p1 <= regfile[4'ha];
	p2 <= regfile[4'hb];
	p1_score <= regfile[4'hc];
	p2_score <= regfile[4'hd];
	// check if reset active
	if (reset)
		//reset regs
		begin
		regfile[4'h0] <= 16'h0000;
		regfile[4'h1] <= 16'h0000;
		regfile[4'h2] <= 16'h0000;
		regfile[4'h3] <= 16'h0000;
		regfile[4'h4] <= 16'h0000;
		regfile[4'h5] <= 16'h0000;
		regfile[4'h6] <= 16'h0000;
		regfile[4'h7] <= 16'h0000;
		regfile[4'h8] <= 16'h0000;
		regfile[4'h9] <= 16'h0000;
		regfile[4'ha] <= 16'h0000;
		regfile[4'hb] <= 16'h0000;
		regfile[4'hc] <= 16'h0000;
		regfile[4'hd] <= 16'h0000;
		regfile[4'he] <= 16'h0000;
		regfile[4'hf] <= 16'h0000;
		
		// FLAGS
		//	Flags = 5'b00000;
		end
		
	else if (wr_en) // write enabled
		begin
		regfile[write_address] <= write_data;
		end
		

end

//   assign Flags = Flags_in;
	assign read_data1 = regfile[rd_address1];
   assign read_data2 = regfile[rd_address2];
	
// If you continue...bad things might happend...ok not really.
endmodule
